NI LabVIEW 8.2.1 FPGA Module Readme
This file contains important last-minute information about the LabVIEW FPGA Module, Version 8.2.1.
The LabVIEW FPGA Module 8.2.1 supports the following platforms:
- Windows XP Professional (Service Packs 2, 3, and 4)
- Windows 2000 Professional (Service Packs 1 and 2)
- Windows Vista Business (32-bit versions). However, the Xilinx tools do not officially support Windows Vista. National Instruments obtained permission from Xilinx to allow LabVIEW FPGA Module customers to use the tools on Windows Vista, with the disclaimer that Xilinx will not be able to fix any bugs found that are specific to the Windows Vista OS. National Instruments tested the Xilinx tools, as they are used by the LabVIEW FPGA Module, and did not find any issues related to Windows Vista. If you encounter problems with the Xilinx tools specific to Windows Vista, you might be required to compile using Windows XP or Windows 2000. National Instruments will not be liable for any problems or issues related to the use of Xilinx tools with Windows Vista.
You must install LabVIEW 8.2.1 before you install the LabVIEW FPGA Module 8.2.1. Refer to the LabVIEW FPGA Module Release and Upgrade Notes for more information about installation instructions. The LabVIEW FPGA Module Release and Upgrade Notes is included as a booklet with the kit. You also can access this document directly from the installation CD or after installation by selecting Help»Search the LabVIEW Help in LabVIEW and navigating to the FPGA Module»FPGA Module Related Documentation topic on the Contents tab.
LabVIEW FPGA Module 8.2.1 includes the following bug fixes:
|43E9O5NR||Fixed an issue where the Memory Read function returned corrupt data.|
|40LCFJ83||Fixed an issue where the FIFO Read, FIFO Write, Memory Read, and Memory Write functions did not refer to the correct FIFO or memory item during emulation.|
|443CEOLJ||Fixed an issue where the Analog Period Measurement, Butterworth, and DC-RMS VIs did not script on Windows XP if the user did not have administrator privileges.|
The following sections describe known issues at the time of release. Refer to the Knowledge Base at ni.com for the most recent information about known issues.
Issues with Importing FPGA Module 1.x Files
- Import utility changes the size of FPGA FIFOs that use block RAM—The import utility causes the FPGA FIFOs using block memory to change size. Right-click the FPGA FIFO in the Project Explorer window and select Properties from the shortcut menu to view the newly configured depth of the FIFO.
- Imported host VI broken—The host VI might import improperly to LabVIEW 8.2.1 if any of the following conditions apply: you use constants for the HW Exec Ref parameter on the block diagram, you use Call By Reference Nodes that pass the HW Exec Ref parameter, or you use strict type definitions of the HW Exec Ref parameter with property nodes to get or set their value. Open the host VI and manually replace all instances of the HW Exec Ref that are broken with the new HW Exec Ref coming from the Open FPGA VI Reference.
- Imported FPGA VI broken—The FPGA VI might import improperly to LabVIEW 8.2.1 if any of the following conditions apply: you have multiple aliases pointing to the same resource or you have aliases with the same name that point to different resources. Edit the resources in the Project Explorer window.
- Importing FPGA Module 1.0 VIs broken due to missing flag for Autopreallocate arrays and strings—An FPGA VI created with the FPGA module 1.0 might be broken after importing the VI to LabVIEW 8.2.1. Make sure that a checkmark appears in the Autopreallocate arrays and strings checkbox. You can find the checkbox by navigating to the Execution category of the VI Properties dialog box for the FPGA VI.
- Import utility replaces Abort method with Reset method—A host VI created with the FPGA module 1.x might have used the Abort method with an Invoke Method function or as part of the Close FPGA VI Reference. The import utility replaces the Abort method with the Reset method. The Abort method in the FPGA Module 1.x reset the FPGA VI to default values. The Reset method in the FPGA Module 8.2.1 resets the FPGA VI to default values. In the FPGA Module 8.2.1, the Abort method stops the FPGA VI but does not reset the values to their default values. By replacing the Abort method with the Reset method, the import utility preserves behavior of your program. No action on your part is necessary.
- Disable legacy USB support on PXI Embedded Real-Time controllers—You must disable Legacy USB Support in the BIOS of PXI Embedded Real-Time Controllers when you use the FPGA Interface functions. Specific controllers affected are the PXI-817x controllers and any other third-party systems that use the PhoenixBIOS. Failure to do so can result in the Open FPGA VI Reference function failing to download the FPGA VI without returning an error. Subsequent reads using the Read/Write Control function return values where all bits of the data type are set to 1 without an error. National Instruments also recommends disabling Legacy USB Support when you use the LabVIEW Real-Time Module to reduce jitter. Disable Legacy USB support by configuring the BIOS of the controller. Refer to the Configuring RT Target Settings topic in the LabVIEW Help for information about configuring the BIOS.
- TCP must be installed—Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server. Refer to the Knowledge Base, for more information about manually installing TCP support.
- FPGA FIFO reset behavior—When you use an FPGA target emulator, FPGA FIFOs reset when the VI is stopped and then started again. When you use an FPGA target with Interactive Front Panel Communication, FPGA FIFOs do not reset when the FPGA VI is stopped and then started again. To reset the FIFO, right-click the FPGA target in the Project Explorer window and select Reset from the shortcut menu. When you control an FPGA VI using Programmatic FPGA Interface Communication, use the Close FPGA VI Reference function with the Close and Reset shortcut menu option selected or the Invoke Method with the Reset method selected to reset FPGA FIFOs.
- Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server—If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality. Refer to the KnowledgeBase for more information about correcting this problem.
- Slow installation/uninstallation progress—If you click the Modify button in the National Instruments Software dialog box, available in the Add or Remove Programs utility, after you install the LabVIEW FPGA Module, the installer can take up to 10 minutes to initialize without any change in the progress indicator bar.
- Opening host VIs that include the FPGA Interface functions take several minutes to open—Host VIs that contain the FPGA Interface functions might take a long time to open because the FPGA Interface functions need several support files to manage the interface with FPGA VIs. The FPGA Interface functions also verify the status of the FPGA VI when you open the host VI.
- New defaults for compile warning dialog boxes—By default, the FPGA Module no longer shows the Beginning Compile dialog box or Possible Inconsistencies dialog box, which appears when you choose to use a previously compiled FPGA VI bitfile rather than recompile the FPGA VI. Use the FPGA Module Options dialog box to change the default settings. Select Tools»FPGA Module Options to display the FPGA Module Options dialog box.
- VI compilation summary now available after compilation—The Target-Specific VI Properties dialog box now includes a compilation summary. You can use this summary to view the size (device utilization) and timing information for the last compilation. You also can use this summary to determine if you must recompile the VI. Right-click a VI under an FPGA target in the Project Explorer window and select Target-Specific Properties from the shortcut menu to display this dialog box.
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