为什么我的FPGA程序在编译时会给出OVERMAPPED的错误?
主要软件:
主要软件版本: 1.1
主要软件修正版本: N/A
次要软件: N/A
问题: 我已经成功编译过我的FPGA代码,但最近我添加了一些代码再次编译时得到一个OVERMAPPED的错误?这是为什么呢?
解答: OVERMAPPED的意思是您的代码需要的资源数量已经超过了FPGA本身具有的资源数量。这样的问题您可以在FPGA的错误日志文件:xflow.log中找到。
一个典型的OVERMAPPED错误如下所示(记住这仅仅在日志文件的末尾):
......
Design Summary:
Number of errors: 1
Number of warnings: 0
Number of Slices: 5,804 out of 5,120 113% (OVERMAPPED)
Number of Slices containing
unrelated logic: 2,017 out of 5,804 34%
Number of Slice Flip Flops: 7,457 out of 10,240 72%
Total Number 4 input LUTs: 9,847 out of 10,240 96%
Number used as LUTs: 9,235
Number used as a route-thru: 612
Number of bonded IOBs: 168 out of 324 51%
IOB Flip Flops: 57
Number of GCLKs: 1 out of 16 6%
Total equivalent gate count for design: 125,437
Additional JTAG gate count for IOBs: 8,064
Peak Memory Usage: 159 MB
Mapping completed.
See MAP report file "toplevel_gen_map.mrp" for details.
Problem encountered during the packing phase.
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
Slice是FPGA资源的基本单位。如果您的代码在优化后需要的slice数量超过了FPGA本身具有的slice数量,那么您的代码将不能适配目标FPGA,您将得到一个编译错误。要获得更多有关Slice的信息,请见下面的链接。
相关链接: KnowledgeBase 2ZUA4DFL. What is the Definition of Logic Cells, Logic Slices, Configurable Logic Blocks and Gates?
KnowledgeBase 3W4CJJXJ
. How Can I Optimize/Reduce FPGA Resource Usage?
附件:
报告日期: 10/03/2006
最近更新: 10/09/2006
文档编号: 38S79L9U
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