Virtex5和Kintex7FlexRIO FPGA模块的引脚分配
硬件: Modular Instruments>>FlexRIO>>PXI-7952R, Modular Instruments>>FlexRIO>>PXIe-7972R, Modular Instruments>>FlexRIO>>PXIe-7961R, Modular Instruments>>FlexRIO>>PXI-7953R, Modular Instruments>>FlexRIO>>PXIe-7963R, Modular Instruments>>FlexRIO>>PXIe-7962R, Modular Instruments>>FlexRIO>>PXIe-7965R, Modular Instruments>>FlexRIO>>PXI-7954R, Modular Instruments>>FlexRIO>>PXI-7951R, Modular Instruments>>FlexRIO>>PXIe-7971R, Modular Instruments>>FlexRIO>>PXIe-7975R
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问题: 需要修改FlexRIO模块的socket CLIP，但是不知道GPIO的引脚定义
解答:
修改FlexRIO模块的socket CLIP时，附件中的excel文件可以用于引脚分配的参考。该文档可以根据下列方式进行排序：
Pin Number
Pin Name
FPGA Pin V5
FPGA Pin K7
V5 ClockCapable?
K7 ClockCapable?
V5 GPIO?
K7 GPIO?
V5 Bank
K7 Bank
例图：
相关链接:
附件:
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报告日期: 07/24/2014
最近更新: 02/27/2015
文档编号: 6NND5NOA