Issue compiling FPGA application at 80MHz derived clock

Mino71 · ‎06-06-2013

Hi all, I'm sorry for my bad english.

I'm a student in Electronic Ingeneering and this is my first time that I work with LabVIEW FPGA. I need to compile a VI with 80MHz derived clock as top level clock, in order to implement a butterworth filter faster than with default 40MHz clock. But when I compile the VI I have an error due to timing contraint and it seems that this is caused by the Analog Digital Converter used.

How can I fix this issue?

I'm using a NI cRIO-9024, A/D converter NI-9223, D/A converter NI-9263 and chassis NI-9118.

I've attached part of my VI.

Thank you all.

Giacomo Bartolini

MHoffmann · ‎06-06-2013

Hi,

could you please attach the detailed error message?

Thanks!

Regards,

Michael

Mino71 · ‎06-06-2013

Hi, I haven't the project in this computer, so I will attach the error message as soon as possible. Thank you for now!

Cla_Cup · ‎06-07-2013

Hi,

you can try to change the compiling options. Right click on FPGA build specification, select properties and change the compiling option.

You'll be able to optimize compilation selecting timing performance optimization.

After that, try to recompile FPGA code.

Best regards.

Cla_CUP

Mino71 · ‎06-10-2013

hi all, the option "timing performance optimization" was already chosen.

The error message occured is: The compilation failed due to timing violations. Labview highlights the part of the code implementing data acquisition through NI 9263 module. I have attacched a jpeg image showing the error messages and the part of the code that labview haighlights.

Best regards.

G.B.

MHoffmann · ‎06-11-2013

Here are two links that maybe could help you:

Fixing Timing Violations (FPGA Module)

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_fix_timing_violations/

Understanding Timing Considerations for FPGA VIs

http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/registers/

Mino71 · ‎06-12-2013

Hi, I've looked at these link, but I've not found any helpful suggestion. This is becouse of the block "Generate I/O Sample Pulse Function" that I can't modify in any way. I've tried to include this function in a SCTL at 40MHz, but my target doesn't support this block inside a SCTL.

Are in labview FPGA the possibilities to implement part of the code with 40MHz clock and part of the code with 80MHz clock ? I ask this becouse I started to think that the block "Generate I/O Sample Pulse Function" can't be implemented with 80MHz clock, so I could implement the acquisition with 40MHz clock and the rest of the application at 80MHz.

Thanks

G.B.

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