Known Issues and Bug Fixes for LabVIEW 8.5.x FPGA Module

Primary Software: LabVIEW Modules>>FPGA Module
Primary Software Version: 8.5
Primary Software Fixed Version: N/A
Secondary Software: N/A

Problem:
What are the known issues and bug fixes for the LabVIEW 8.5.x FPGA Module?

Solution:

Known Issues

The following sections describe known issues at the time of the FPGA Module 8.5.x release.

Installation Issues
Issues with Importing FPGA Module 1.x Files
General Issues
Host VI Issues
Documentation Issues

Installation Issues

TCP must be installed—Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server.
Incorrect mutation—You must install LabVIEW 8.5.x and then the FPGA Module 8.5.x before you mass compile existing VIs. If you mass compile existing VIs before you install the FPGA Module 8.5.x, the following VIs might have mutation issues: Sine Wave Generator, Discrete Delay, Quantizer, Saturation Add, Saturation Subtract, Saturation Multiply, Look-Up Table 1D, Analog Period Measurement, Butterworth Filter, FIFO Read, FIFO Write, HDL Interface Node, Open FPGA VI Reference, Read/Write Control, Call VI, Close FPGA VI Reference, Invoke Method, Up Cast, FPGA I/O Method Node, and FPGA I/O Property Node.

Issues with Importing FPGA Module 1.x Files

Import utility changes the size of FPGA FIFOs that use block RAM—The import utility causes the FPGA FIFOs using block memory to change size. Right-click the FPGA FIFO in the Project Explorer window and select Properties from the shortcut menu to view the newly configured depth of the FIFO.
Imported host VI broken—The host VI might import improperly to LabVIEW 8.5.x if any of the following conditions apply: you use constants for the HW Exec Ref parameter on the block diagram, you use Call By Reference Nodes that pass the HW Exec Ref parameter, or you use strict type definitions of the HW Exec Ref parameter with property nodes to get or set their value. Open the host VI and manually replace all instances of the HW Exec Ref that are broken with the new HW Exec Ref from the Open FPGA VI Reference function.
Imported FPGA VI broken—The FPGA VI might import improperly to LabVIEW 8.5.x if any of the following conditions apply: you have multiple aliases pointing to the same resource or you have aliases with the same name that point to different resources. Edit the resources in the Project Explorer window.
Importing FPGA Module 1.0 VIs broken due to missing flag for Autopreallocate arrays and strings—An FPGA VI created with the FPGA Module 1.0 might be broken after importing the VI to LabVIEW 8.5.x. Make sure that a checkmark appears in the Autopreallocate arrays and strings checkbox. You can find the checkbox by navigating to the Execution category of the VI Properties dialog box for the FPGA VI.
Import utility replaces Abort method with Reset method—A host VI created with the FPGA module 1.x might have used the Abort method with an Invoke Method function or as part of the Close FPGA VI Reference. The import utility replaces the Abort method with the Reset method. The Abort method in the FPGA Module 1.x reset the FPGA VI to default values. The Reset method in the FPGA Module 8.5.x resets the FPGA VI to default values. In the FPGA Module 8.5.x, the Abort method stops the FPGA VI but does not reset the values to their default values. By replacing the Abort method with the Reset method, the import utility preserves behavior of your program. No action on your part is necessary.

General Issues

Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server—If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality. Refer to the KnowledgeBase for more information about correcting this problem.
FPGA FIFO reset behavior—When you use an FPGA target emulator, FPGA FIFOs reset when the VI is stopped and then started again. When you use an FPGA target with Interactive Front Panel Communication, FPGA FIFOs do not reset when the FPGA VI is stopped and then started again. To reset the FIFO, right-click the FPGA target in the Project Explorer window and select Download from the shortcut menu. When you control an FPGA VI using Programmatic FPGA Interface Communication, use the Close FPGA VI Reference function with the Close and Reset shortcut menu option selected or the Invoke Method with the Reset method selected to reset FPGA FIFOs.
Multiplying fixed-point data might not meet 40 MHz timing If you use the Multiply function with inputs above 32 bits that contain fixed-point data, the function might not meet 40 MHz timing requirements. You can place the Multiply function inside a single-cycle Timed Loop that is configured at a lower clock rate.
Saving to LabVIEW 8.0—The FPGA Module 8.5.x does not support saving to LabVIEW 8.0. You can save to LabVIEW 8.2 and then save to LabVIEW 8.0.
Saving FIFOs from FPGA Module 8.5.1 to FPGA Module 8.5—If you include FIFOs in an FPGA VI that you create using the FPGA Module 8.5.1, the FPGA VI is broken if you open it in the FPGA Module 8.5. You must replace the FIFOs and save the FPGA VI to FPGA Module 8.2.1 to open the FPGA VI in LabVIEW 8.5.

Host VI Issues

Host VIs with VISA name controls—The Open FPGA VI Reference function no longer supports VISA name controls. When you open an existing host VI that uses a VISA name control, the FPGA Module includes a Concatenate Strings function on the block diagram to allow the VI to work with the Open FPGA VI Reference function, which requires an NI-RIO name control. You can remove the Concatenate Strings function if you change the VISA name control to an NI-RIO name control.
Opening host VIs that include the FPGA Interface functions take several minutes to open—Host VIs that contain the FPGA Interface functions might take a long time to open because the FPGA Interface functions need several support files to manage the interface with FPGA VIs. The FPGA Interface functions also verify the status of the FPGA VI when you open the host VI.
Disable legacy USB support on PXI Embedded Real-Time controllers—You must disable Legacy USB Support in the BIOS of PXI Embedded Real-Time controllers when you use the FPGA Interface functions. Specific controllers affected are the PXI-817x controllers and any other third-party systems that use the PhoenixBIOS. Failure to disable Legacy USB Support can result in the Open FPGA VI Reference function failing to download the FPGA VI without returning an error. Subsequent reads using the Read/Write Control function return values where all bits of the data type are set to 1 without an error. National Instruments also recommends disabling Legacy USB Support when you use the LabVIEW Real-Time Module to reduce jitter. Disable Legacy USB support by configuring the BIOS of the controller. Refer to the Configuring RT Target Settings topic in the LabVIEW Help for information about configuring the BIOS.

Documentation Issues

Support for 64-bit Windows Vista—The LabVIEW FPGA Module Release and Upgrade Notes lists only the 32-bit version of Windows Vista as supported. However, the FPGA Module also supports the 64-bit version of Windows Vista.
Default for host part of FIFOs—The Transferring Data Between the FPGA and the Host VI topic in the LabVIEW Help states "If you do not specify the size of the host computer part of the FIFO in the host VI, the host computer part size defaults to twice the size of the FPGA part of the FIFO." However, the default is actually 10,000 elements.

Bug Fixes

The following items are the IDs and titles of a subset of issues fixed in the FPGA Module 8.5.1.

Bug ID	Fixed Issue
4D4G2K00	LabVIEW hangs opening FPGA host VI when there is a subVI or typedef listed as missing under Dependencies for the FPGA target.
4DCC5368	Connecting FPGA VI reference to Read/Write Control function hangs LabVIEW because there is not enough memory to complete this operation.
4C08H4P2	Sine Generator VI output overflows for full-scale sine waves.
4CTM7TJ0	Placing FPGA VI using the Wait on Occurrence with Timeout in Ticks function in a project library file (.lvlib) causes Xilinx to fail compilation with program map error.

The following items are the IDs and titles of a subset of issues fixed in the FPGA Module 8.5.

Bug ID	Fixed Issue
478E06KQ	Code generation error from memory, FIFO, and FPGA I/O items if item name in Project Explorer window changes case while the VI is out of memory.
496932KQ	FPGA VI needs to be saved every time it is opened.
48GMNK8R	FPGA case structure doesn't work when signed negative numbers or 64-bit numbers are connected to case selector.
47RCEBLJ	Host interface can't read an FPGA indicator that is a typedef in a library.
43J8K1LJ	Interactive mode does not update front panel control as expected.
3X8HQKLJ	Compile fails when HDL Interface Node references a .vhd file that has repetitious library.
3V57R3LJ	Objects with embedded shift registers should allow the user to set an initial value.
3KP5PPTP	Unable to pass occurrence to subVI.

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Report Date: 06/29/2007
Last Updated: 08/27/2008
Document ID: 4ASEPOHB

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