What are the Valid Phase-Lock Looping Reference Clock Parameters for Modular Instruments? Hardware: Signal Sources (AWG/FG/AO)>>Arbitrary Waveform and Function Generators>>PXI-5421
Problem: I need to Phase-Lock Loop (PLL) my reference clock on my Modular Instrument, what are the valid values that I can use? Solution: Most Modular Instrument devices can PLL to a reference clock source from the external connector, from RTSI Osc (RTSI 7) on the RTSI bus (for PCI devices), or from the 10 MHz PXI_CLK10 clock line on the PXI trigger bus (for PXI device). The frequency stability of the sample clock matches that of the PLL reference clock when the two are phase locked. In turn, phase locking synchronizes clocks of multiple devices that are phase locked to the same reference clock. The valid reference clock frequency and signal level depend on the devices you are using. Valid reference clock frequency and signal level of some devices when using external connector are listed below: Arbs: 5401: 1 MHz or 5–20 MHz in 1 MHz steps; 1 Vpk-pk to 5 Vpk-pk 5404: 3 MHz to 20 MHz in 1 MHz increments; 250 mVpk-pk to 5 Vpk-pk 5411/5431: 1 MHz or 5–20 MHz in 1 MHz steps; 1 Vpk-pk to 5 Vpk-pk 5421: 5MHz to 20MHz in increments of 1MHz. Default of 10 MHz; 0.2 Vpk-pk to 2.8 Vpk-pk Digitizer: 5102: Do not need PLL 5112/5911: 10MHz; TTL. 5620/5621: 10MHz; –5 dBm to +15 dBm 5122: 1 MHz to 20 MHz in 1 MHz increments, Default of 10 MHz; 0.2 Vpk-pk to 2.8 Vpk-pk HSDIO: 655x: 10MHz, 0.65 Vpp to 2.8 Vpp RF Downconverter: 5600: 10MHz In addition to frequency and signal level requirements, most Modular Instruments also impose an accuracy requirement on the PLL reference clock. For more detailed information, please refer to the specific devices' users manual. Related Links: National Instruments Product Manuals Attachments:
Report Date: 03/10/2004 Last Updated: 04/16/2004 Document ID: 379AM3FE |
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