How do I set the Rate of a Timed Loop on an FPGA TargetPrimary Software: LabVIEW Modules>>LabVIEW FPGA ModulePrimary Software Version: 8.2 Primary Software Fixed Version: N/A Secondary Software: N/A
Problem: My FPGA code contains a timed loop structure. I've set the Period (dt) of my loop to 100 ticks of the 40MHz clock. However, when I compile and run my FPGA code, the loop seems to run at a full 40MHz without waiting the 100 ticks between loop cycles like I specified. Why is this happening? Solution: On an FPGA target, the timed loop structure can only run as a single cycle timed loop. The only parameter that matters is the Timing Source. The timing source is the 40MHz FPGA clock by default, but a derived clock can be chosen as well. Every other parameter that is set such as period (dt), offset, timeout, and deadline is ignored by the compiler. In LabVIEW 8.6, the only input available on the timed loop is the Source Name. If you want to implement other custom timing options, you can use a while loop with either a loop timer, wait function, or sequence structure in order to time your execution. Examples of these implementations are shown below.  Related Links: KnowledgeBase 42OGRRTQ: Single-Cycle Timed Loop FAQ for the LabVIEW FPGA Module Attachments:
Report Date: 10/28/2006 Last Updated: 07/17/2009 Document ID: 42RBUICW |
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