Timing Constraint Error in LabVIEW FPGA 8.6Primary Software: LabVIEW Modules>>FPGA ModulePrimary Software Version: 8.6 Primary Software Fixed Version: N/A Secondary Software: Driver Software>>NI-RIO
Problem: I tried to compile a LabVIEW FPGA VI but it fails with a timing constraint error similar to this; ======================================================================= Timing constraint: TS_ TheWindowx_RioClk40Derived29x23ClkFXFromDCM1 = PERIOD TIMEGRP "TheWindowx_RioClk40Derived29x23ClkFXFromDCM1" TS_RioClk40pin / 1.26 HIGH 50%; 20 items analyzed, 2 timing errors detected. (1 setup error, 1 hold error) Minimum period is 26310.429ns. ----------------------------------------------------------------------- How do I fix this error? Solution: To fix this error, extract the attached zipped file to
labview\rvi\HDL\NiCores\ClockBoundaryCrossing\Source\DoubleSync.
Select Yes when prompted to replace the existing file.
Related Links: Attachments:  DoubleSyncBase.zip
Report Date: 09/18/2008 Last Updated: 09/18/2008 Document ID: 4PHGA62M |
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