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LabVIEW FPGA Module 8.6 Readme

Primary Software: LabVIEW Modules>>FPGA Module
Primary Software Version: 8.6
Primary Software Fixed Version: N/A
Secondary Software: N/A

Problem:
What are the known issues and bug fixes for the LabVIEW 8.6 FPGA Module?

Solution:

Known Issues

The following sections describe known issues at the time of the FPGA Module 8.6 release.

Installation Issues
Issues with Importing FPGA Module 1.x Files
General Issues
Host VI Issues

Installation Issues

  • TCP must be installed—Most Windows installations have TCP installed. The LabVIEW FPGA Module communicates with the LabVIEW FPGA Compile Server through TCP. If TCP is not installed, LabVIEW returns the Error Contacting Server message when it attempts to contact the LabVIEW FPGA Compile Server.
  • Incorrect mutation—You must install LabVIEW 8.6 and then the FPGA Module 8.6 before you mass compile existing VIs. If you mass compile existing VIs before you install the FPGA Module 8.6, the following VIs might have mutation issues: Sine Wave Generator, Discrete Delay, Quantizer, Saturation Add, Saturation Subtract, Saturation Multiply, Look-Up Table 1D, Analog Period Measurement, Butterworth Filter, FIFO Read, FIFO Write, HDL Interface Node, Open FPGA VI Reference, Read/Write Control, Call VI, Close FPGA VI Reference, Invoke Method, Up Cast, FPGA I/O Method Node, and FPGA I/O Property Node.

Issues with Importing FPGA Module 1.x Files

  • Import utility changes the size of FPGA FIFOs that use block RAM—The import utility causes the FPGA FIFOs using block memory to change size. Right-click the FPGA FIFO in the Project Explorer window and select Properties from the shortcut menu to view the newly configured depth of the FIFO.
  • Imported host VI broken—The host VI might import improperly to LabVIEW 8.6 if any of the following conditions apply: you use constants for the HW Exec Ref parameter on the block diagram, you use Call By Reference Nodes that pass the HW Exec Ref parameter, or you use strict type definitions of the HW Exec Ref parameter with property nodes to get or set their value. Open the host VI and manually replace all instances of the HW Exec Ref that are broken with the new HW Exec Ref from the Open FPGA VI Reference function.
  • Imported FPGA VI broken—The FPGA VI might import improperly to LabVIEW 8.6 if any of the following conditions apply: you have multiple aliases pointing to the same resource or you have aliases with the same name that point to different resources. Edit the resources in the Project Explorer window.
  • Importing FPGA Module 1.0 VIs broken due to missing flag for Autopreallocate arrays and strings—An FPGA VI created with the FPGA Module 1.0 might be broken after importing the VI to LabVIEW 8.6. Make sure that a checkmark appears in the Autopreallocate arrays and strings checkbox. You can find the checkbox by navigating to the Execution category of the VI Properties dialog box for the FPGA VI.
  • Import utility replaces Abort method with Reset method—A host VI created with the FPGA module 1.x might have used the Abort method with an Invoke Method function or as part of the Close FPGA VI Reference. The import utility replaces the Abort method with the Reset method. The Abort method in the FPGA Module 1.x reset the FPGA VI to default values. The Reset method in the FPGA Module 8.6 resets the FPGA VI to default values. In the FPGA Module 8.6, the Abort method stops the FPGA VI but does not reset the values to their default values. By replacing the Abort method with the Reset method, the import utility preserves behavior of your program. No action on your part is necessary.

General Issues

  • Windows XP Service Pack 2 displays security alert when you launch the LabVIEW FPGA Compile Server—If you have Windows XP Service Pack 2 installed, a security alert dialog box appears when you launch the LabVIEW FPGA Compile Server for the first time. If you select the Keep blocking this program option, the LabVIEW FPGA Compile Server cannot accept incoming connections from a remote computer. Select Unblock this program, despite the security risk to configure your computer to launch the LabVIEW FPGA Compile Server without any changes in server functionality. Refer to the KnowledgeBase for more information about correcting this problem.
  • FPGA FIFO reset behavior—When you use an FPGA target emulator, FPGA FIFOs reset when the VI is stopped and then started again. When you use an FPGA target with Interactive Front Panel Communication, FPGA FIFOs do not reset when the FPGA VI is stopped and then started again. To reset the FIFO, right-click the FPGA target in the Project Explorer window and select Download from the shortcut menu. When you control an FPGA VI using Programmatic FPGA Interface Communication, use the Close FPGA VI Reference function with the Close and Reset shortcut menu option selected or the Invoke Method with the Reset method selected to reset FPGA FIFOs.
  • Multiplying fixed-point data might not meet 40 MHz timing—If you use the Multiply function with inputs above 32 bits that contain fixed-point data, the function might not meet 40 MHz timing requirements. You can place the Multiply function inside a single-cycle Timed Loop that is configured at a lower clock rate.
  • Saving to LabVIEW 8.0—The FPGA Module 8.6 does not support saving to LabVIEW 8.0. You can save to LabVIEW 8.2 and then save to LabVIEW 8.0.
  • Adding CLIP from a network returns internal error—If you add a component-level IP (CLIP) declaration XML file to a project from a network location, the FPGA Module returns an internal error when you create an instance of the declaration.
  • Interrupt VIs saved to previous versions of LabVIEW are broken—If you save an FPGA VI that contains an Interrupt VI to a previous version of LabVIEW and open the FPGA VI in a previous version of LabVIEW, the FPGA VI is broken because the Interrupt VI is not executable. You can delete the Interrupt VI and replace it with an Interrupt VI from the current version to resolve the issue.
  • Read/Write Control function allows you to select disabled control—If you disable a control, you can still select the control from the Read/Write Control function, which returns error -61059.
  • Modifying conditional disable symbols requires recompile—If you modify the conditional disable symbols in a project, the FPGA Module requires you to recompile the FPGA VI even if the FPGA VI does not use Conditional Disable structures.
  • Large frequency changes cause incorrect states in Notch Filter and Butterworth Filter VIs—If you change frequency significantly at run time, the VIs might return incorrect states. Change the frequency gradually or reset after changing the frequency.
  • Error compiling empty external clock loop—If you compile an FPGA VI that contains only an empty loop configured to use an external clock, the FPGA Module returns an error.
  • Compiling while the Code Generation Errors window is open from another project returns error—Close the Code Generation Errors window before compiling.
  • Configuration dialogs requiring a sample rate do not coerce to a legal FPGA loop rate—The Expected sample rate (S/s) parameter on the configuration dialog box of the Notch Filter, Butterworth Filter, and DC and RMS Measurements VIs must match the loop rate the VI is called at in the FPGA VI. You must ensure that the sample rate you enter is a factor of 40 MHz (for example, 40 MHz/50kS/s = 800 ticks).
  • Password required when saving project for previous—If the FPGA target is configured to run FPGA VIs on the development computer and you save the project for a previous version of LabVIEW, LabVIEW prompts you to enter a password. Before you save for previous, make sure the FPGA devices are targeted to actual hardware.
  • Unable to find typedef when using custom VI—LabVIEW might return load warnings if you create a custom VI for FPGA I/O using the template VI, move the custom VI to different location, and open the custom VI. Ignore the warning messages and resave the VI.
  • Control VIs were not mutated—Previous instances of these VIs continue to work. However, if you replace these VIs with the 8.6 version of these VIs, terminal names, single-cycle Timed Loop support, and fixed-point support might vary.
  • Converting Analysis VIs to subVI removes terminal default values—If you create a subVI from the Analog Period Measurement, Butterworth Filter, Notch Filter, or PID (FPGA) VI, some terminal default values might not remain.
  • Butterworth Filter VI configuration is not mutated—If the Butterworth Filter VI is configured with sample rates more than 100 times the cutoff frequency and the Show configuration terminal option is checked, the FPGA Module does not mutate the VI and the configuration dialog box is not available. This configuration uses an accuracy-optimized implementation that is not reconfigurable and is not supported with the configuration terminal shown in the FPGA Module 8.6. To use an equivalent but non-reconfigurable filter in the FPGA Module 8.6, use a new Butterworth Filter VI with the same filter parameters and no configuration terminal shown.

Host VI Issues

  • Cannot build installer if host VI references FPGA VI—If the Open FPGA VI Reference function refers to an FPGA VI, you might not be able to build an installer. You can configure the Open FPGA VI Reference function to refer to a bitfile to create an installer.
  • Host VI does not get notified of changes when building an application—If you make changes to an FPGA VI without saving the host VI, the host VI refers to the old FPGA VI when you build an application. You must open and save the host VI before building an application.
  • Host VIs with VISA name controls—The Open FPGA VI Reference function no longer supports VISA name controls. When you open an existing host VI that uses a VISA name control, the FPGA Module includes a Concatenate Strings function on the block diagram to allow the VI to work with the Open FPGA VI Reference function, which requires an NI-RIO name control. You can remove the Concatenate Strings function if you change the VISA name control to an NI-RIO name control.
  • Opening host VIs that include the FPGA Interface functions take several minutes to open—Host VIs that contain the FPGA Interface functions might take a long time to open because the FPGA Interface functions need several support files to manage the interface with FPGA VIs. The FPGA Interface functions also verify the status of the FPGA VI when you open the host VI.
  • Disable legacy USB support on PXI Embedded Real-Time controllers—You must disable Legacy USB Support in the BIOS of PXI Embedded Real-Time controllers when you use the FPGA Interface functions. Specific controllers affected are the PXI-817x controllers and any other third-party systems that use the PhoenixBIOS. Failure to disable Legacy USB Support can result in the Open FPGA VI Reference function failing to download the FPGA VI without returning an error. Subsequent reads using the Read/Write Control function return values where all bits of the data type are set to 1 without an error. National Instruments also recommends disabling Legacy USB Support when you use the LabVIEW Real-Time Module to reduce jitter. Disable Legacy USB support by configuring the BIOS of the controller. Refer to the Configuring RT Target Settings topic in the LabVIEW Help for information about configuring the BIOS.
  • Error checking on Read/Write Control function—The FPGA Module checks the Read/Write Control function to see if the timeout bit is set after all of the reads/writes have completed. However, race conditions for when the error message gets reported might exist. As a result, the FPGA Module might return the error on a Read/Write Control function other than the Read/Write Control function where the error occurred.

Bug Fixes

The following items are the IDs and titles of a subset of issues fixed in the FPGA Module 8.6.

Bug ID Fixed Issue
107867 Butterworth 32-bit response is incorrect for small input signals.
68173 Code generation errors (1099) with Disable/Conditional Disable Structure.
59157 Compile error xflow-6 with FPGA VI calling a subVI with unconnected I/O control.
58593 FPGA compiler crash when writing to one and the same global variable in multiple single-cycle Timed Loops.
53162 Compiling multichannel PID Express VI in While Loop fails due to timing violation.
42442 Timing violation with target-scoped FIFO configured with depth of 6 elements.


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Report Date: 06/03/2008
Last Updated: 11/04/2008
Document ID: 4M2H3RLC

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