RTSI Bus Implementation in PXI-DAQ Hardware Hardware: PXI/CompactPCI>>Chassis>>PXI-1010
Problem: How is the RTSI bus implemented in the PXI-DAQ hardware? Solution: The PXI Specification implements the RTSI bus via the PXI trigger lines. PXI Specification requires 8 lines, PXI_TRIGGER[0:7], on the P2/J2 connector for the trigger lines. The RTSI features of the DAQ hardware is implemented on this sub-bus. The RTSI trigger [0..6] is implemented on PXI_TRIGGER[0:6], and the RTSI clock is ROUTED on PXI_TRIGGER(7). SCXI does not use the PXI trigger lines. If you are using the PXI-1010 chassis, slot 8 has connections for a PXI peripheral module to control the SCXI subsystem. These connections use the available local bus right pins (PXI_LBR0:12). The SCXI connection passes communication, timing, and analog signals between the SCXI backplane and the PXI module in slot 8. If you are using the PXI-1011 chassis, slot 4 has connections for a PXI peripheral module to control the SCXI subsystem. These connections use the available local bus right pins (PXI_LBR0:12). The SCXI connection passes communication, timing, and low-voltage analog bus signals between the SCXI subsystem and the PXI module in slot 4. Related Links: Attachments:
Report Date: 02/25/1998 Last Updated: 08/28/2007 Document ID: 16O1D6PV |
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