Is it possible to configure a digital line on an R-series board to a tri-state mode in FPGA?Primary Software: LabVIEW Development Systems>>LabVIEW Full Development SystemPrimary Software Version: N/A Primary Software Fixed Version: N/A Secondary Software: LabVIEW Modules>>FPGA Module
Problem: I would like to be able to configure my DIO lines on a R-series card to a Tri-state mode and keep it in a Single Cycle Timed Loop (SCTL). Is this possible? Solution: The DIO on R-series boards are bidirectional, which means it can be considered as a tri-state DIO. When you add an FPGA I/O Method Node and set the Set Output Enable to True, then the DIO will be configured for output and when it’s set to False (high impedance), the DIO will be configured for input. You must set the Set Output Enable FPGA I/O Method Node line to False in order to read the line as an input otherwise it will read back the written data. Since this Method (Set Output Enable) is supported in a single cycle timed loop, it will be possible to perform the tri-state in one cycle. However, in the low level implementation of this Method, the DIO line, Set Output Enable and Set Output Data each takes one cycle. So in reality, there is an internal pipeline that will be implemented when placed in a SCTL. Hence, depending on the number of stages for the pipeline, the actual data might be off by one or more cycles. The figure below is a sample benchmark performed for this operation. After comparing the state of the "DIO0 In" indicator with the "input State" indicator, the "DIO0 In" was off by one clock cycle.  Related Links: Attachments:  Tri-state.png
Report Date: 10/24/2008 Last Updated: 11/11/2008 Document ID: 4QNHGPL1 |
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