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PXI-1045 and PXI-1006 Trigger and Synchronization Facts



Hardware: PXI/CompactPCI>>Chassis>>PXI-1006

Problem:
What is the architecture of the PXI-1045 and the PXI-1006 18-slot chassis and how do I use the PXI Trigger Lines in these chassis?

Solution:
The PXI-1045 and PXI-1006 chassis are divided into three segments by two PCI-PCI Bridges. The segment divisions are implemented as follows:
  • First segment = slots 1-6
  • (PCI-PCI bridge)
  • Second segment = slots 7-12
  • (PCI-PCI bridge)
  • Third segment = slots 13-18


Each segment has 8 PXI Trigger Lines that are not connected across segments. The two bridges contain buffering for the 8 line PXI Trigger Bus that must travel across the bridges (Note: this is the bus that NI uses to implement RTSI, this is not the star trigger). This buffering is done by the PCI-PCI bridge to ensure performance and is required by the PXI specification. Because of this buffering, the trigger lines are directionally dependent. To accommodate this directional dependence and allow the user to implement different triggering schemes, the PXI-1045 and PXI-1006 have built-in switching so that you may change the direction of the PXI Trigger Bus. Software is required to change the direction of the PXI Trigger Bus. This software is available in Measurement & Automation Explorer. For more information on how to use it, please refer to the Routing PXI Trigger Lines Across the Buses of Multisegment PXI Chassis KnowledgeBase article linked below.

The PXI Star Trigger is another triggering feature of the PXI specification which can be used in the PXI-1045 and PXI-1006 chassis. This trigger is separate from the PXI Trigger Bus. It is a very precise trigger where the lines are specially routed so that they have equal delays to each slot capable of receiving a star trigger. A device must have Star Triggering capabilities to control this special trigger. Slot 2 of your PXI chassis is the Star Trigger controller slot. The Star Trigger in a PXI-1045 and PXI-1006 chassis is routed from this slot to slots 3-15. The last 3 slots of the PXI-1045 and PXI-1006 chassis do not have Star Trigger capabilities because the Star Trigger Bus is limited to 13 lines by the PXI specification.

The 10MHz clock is present in all slots of the PXI-1045 and PXI-1006 chassis without any configuration.

The PXI Local Bus in the PXI-1045 and PXI-1006 is connected between adjacent slots the same way they are in all other PXI chassis.

For more information, please refer to the PXI Specification (Hardware) available in the PXI System Alliance web page (see link below).

Here is a slot by slot overview of what is done in the PXI-1045 and PXI-1006 chassis.

Slot 1 - PXI Controller slot for either an Embedded Computer, MXI-3 or MXI-4 card
Slot 2 - PXI Local Bus, 10 MHz clock, Star Trigger Controller (Not all devices have the ability to be a Star Trigger Controller)
Slot 3 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)
Slot 4 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)
Slot 5 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)
Slot 6 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)

PCI-PCI bridge with trigger buffering for PXI Trigger Bus (software required for using 8 lines of PXI Trigger Bus/RTSI)

Slot 7 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)
Slot 8 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)
Slot 9 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)
Slot 10 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)
Slot 11 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)
Slot 12 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)

PCI-PCI bridge with trigger buffering for PXI Trigger Bus (software required for using 8 lines of PXI Trigger Bus/RTSI)

Slot 13 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)
Slot 14 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)
Slot 15 - PXI Local Bus, 10 MHz clock, Star Trigger Receiver (Not all devices have the ability to be a Star Trigger Receiver)
Slot 16 - PXI Local Bus, 10 MHz clock
Slot 17 - PXI Local Bus, 10 MHz clock
Slot 18 - PXI Local Bus, 10 MHz clock

Related Links:
KnowledgeBase 32GFMIWD: Routing PXI Trigger Lines Across the Buses of Multisegment PXI Chassis?
External Link: PXI System Alliance: PXI Specifications
Product Documentation: How Do National Instruments PXI Boards Map to the PXI Backplane?

Attachments:





Report Date: 09/21/2001
Last Updated: 06/09/2017
Document ID: 2DKAUN00

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