What Is the Basic Architecture for Serial Communication?Primary Software: Driver Software>>NI-SerialPrimary Software Version: 1.0 Primary Software Fixed Version: N/A Secondary Software: N/A
Problem: What is the basic architecture for serial communication? Solution: The core of every asynchronous serial system is a UART (Universal Asynchronous Receiver/Transmitter). The UART not only controls the transfer of data and the appropriate voltage levels, but the speed at which the communication takes place. UARTs increase communication speed and lower system overhead by offering FIFOs (first in first out buffers). With the FIFO buffer, the UART can store enough information that the data stream can continue to transmit even when the computer is busy. This is very helpful for operating systems that do a lot of multitasking. The attached image is an idealized schematic of the serial communication architecture. Most of our serial cards come with an input and output FIFO (check the catalog for details). The data on the FIFO is made available to the serial driver. The serial driver automatically transfers the data from the FIFO to the software buffer that is user configurable from the application software (for example, in LabVIEW you would use the Serial Port Init VI to set the Buffer size parameter). The act of reading a port actually involves reading from this software buffer. This is essentially a double buffer transfer, and you can run the risk of buffer over-runs at both the FIFO and software buffer level. For more information, please refer to the attached VI. Related Links: Developer Zone Tutorial: Serial Communications Hardware Concepts and Hardware Overrun Errors Developer Zone Tutorial: Serial Communication Starting Point Developer Zone Tutorial: Serial Communication Overview Attachments:  Basic Serial Write and Read.vi
Report Date: 11/05/2002 Last Updated: 12/03/2008 Document ID: 2R4FCC5A |
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