NAT9914 Reference Manual Discrepancies Hardware: GPIB>>ASICs/OEM Products
Problem: Are there any typos, misprints, or other errors in the NAT9914 Reference Manual? Solution: Page 3-3 describes the Page-In Condition and states that "Four writable registers can appear at the same offset as the Address Status Register (ADSR) (offset 4)." ADSR is at offset 2, not offset 4. Page 3-15 describes the Auxiliary Command Register (AUXCR) and states that "Writes to the AUXCR should be separated by at least four clock cycles." It would be more accurate to state that "Any access following a write to the AUXCR should be delayed by at least four clock cycles." Page 3-46 of the manual describes the values of bit 2 of the Interrupt Mask Register 2 (IMR2) and the Interrupt Status Register 2 (ISR2). It states that "ATN is cleared by a chip_reset + read ISR0." It should state that "ATN is cleared by a chip_reset + read ISR2." The same error occurs on that page regarding the LLOC bit. The LLOC is cleared by "ch_rst + (read ISR2)" rather than ISR0. Same applies to: "TNT4882 Programmer Reference Manual" page 3-109. Related Links: KnowledgeBase 41DJKCD2: GPIB Register-Level Programming Resources Attachments:
Report Date: 09/25/1997 Last Updated: 05/07/2008 Document ID: 11O7MUQA |
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