How Big Is The Onboard Memory For NI-TIO & DAQ STC Counters? Hardware: Counter/Timers (TIO)
Problem: How big is the onboard memory for NI-TIO & DAQ STC counters? Solution: In general, counters use a count register to store the current count. The count increments or decrements when an edge is detected on the source input. NI-TIO and DAQ STC counters are equipped with two counter registers per counter, software (SW) and hardware (HW). See the image below for more details.  The software register is a copy of the hardware register. This way, the SW register can be queried by the application with software without interrupting the HW register while an operation is in progress. For NI-TIO counters in high speed buffered operations, values are alternately latched from SW and HW registers to a software buffer to achieve maximum transfer rates. In effect, this creates a two sample FIFO for each counter. Using a device with a larger onboard FIFO can increase performance, as described in KB 40TFKJ46: Benchmarks for Buffered Counter Input with M-Series Devices (also linked below). Related Links: KB 2HLA5TXA: Buffered Counter Operations with Counter Boards KB 2JCD04EW: How are Buffers Read in Finite vs. Continuous Buffer Mode for Counter Operations? KB 2C69GDQO: At What Signal Rates Can the Data Acquisition DAQ-STC Counter Chip Acquire? KB 40TFKJ46: Benchmarks for Buffered Counter Input with M-Series Devices Developer Zone: Counter/Timer Hardware Product-Feature Matrix Products and Services: Counter/Timers Product Manuals: DAQ-STC Technical Reference Manual Attachments:
Report Date: 08/03/2007 Last Updated: 08/03/2007 Document ID: 4C2E1H84 |
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