Missing the First Sample with NI-HSDIO Devices Primary Software: Driver Software>>NI-HSDIOPrimary Software Version: 1.0 Primary Software Fixed Version: N/A Secondary Software: N/A Hardware: Digital I/O (DIO)>>High-Speed>>PXI-6552
Problem: I am generating a signal, exporting the clock and reading the signal back. I am triggering the acquisition off the data active event, and if I select to acquire my data on the same edge that it is generated, everything works as expected. However, if I generate the signal on the rising edge and acquire on the falling edge I miss the first sample. For example, if I generate the 8 data points with values {0, 1, 2, 3, 4, 5, 6, 7}, I read back {1, 2, 3, 4, 5, 6, 7, 7}. Why does my HSDIO device miss the first sample? Solution: The behavior described above is expected based on the timing diagram shown below. The first two rising edges of the sample clock are numbered. At the first rising edge, data generation starts and the data active event is fired. These signals do not get generated the instant the clock transitions high. There is a finite amount of time between the rising edge of the sample clock and when the data becomes valid. Since the default position of the start trigger is latched relative to the rising edge of the sample clock, the start trigger is not seen until the second sample clock edge. As shown in the picture below, if the second sample clock rising edge is used to sample the data, the data generated on the first clock edge is latched (sample n). However, if the falling edge of the second sample clock is used, the data generated for the second sample clock is latched (sample n+1). Related Links: Attachments:  
Report Date: 08/27/2006 Last Updated: 09/25/2006 Document ID: 40QJMO17 |
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