Pattern Regeneration with PCI-6534 vs. PCIe-6536/37 Hardware: Digital I/O (DIO)>>High-Speed>>PCIe-6537, Digital I/O (DIO)>>High-Speed>>PXI-6534, Digital I/O (DIO)>>High-Speed>>PCIe-6536
Problem: I have an application developed for the PCI-6534 that performs pattern regeneration by storing a digital pattern in the onboard memory. I am interested in upgrading to the PCIe-6536 or PCIe-6537, but these cards do not have much onboard memory available for pattern storage. Where are patterns stored when performing pattern regeneration with a PCIe-6536/37 and does this affect the performance? Solution: The PCI-6534 devices provide onboard memory in order to perform pattern output at high deterministic rates. The device memory is necessary because the PCI bus does not continuously transfer the pattern data from PC RAM to the digital I/O hardware in a way that would prevent glitches. On the other hand, the PCIe-6536/37 is built for the PCI Express bus and has the ability to transfer large amounts of data at high rates without any glitches. This removes the need for expensive onboard memory, lowering the cost of the digital device. In the case of the PCIe-6536/37, the pattern is stored in PC RAM and is continuously streamed to the board. The PCIe-6536 has a maximum clock rate of 25MHz, and the PCIe-6537 has a maximum clock rate of 50MHz. This is much better performance than the maximum clock rate of 20MHz for the PCI-6534. In addition, NI-DAQmx applications that you currently have developed for the PCI-6534 are compatible with the PCIe-6536/37. Related Links: NI PCI-6534 Specifications NI PCIe-6536/6537 Specifications Attachments:  - image1.jpg
Report Date: 12/15/2006 Last Updated: 04/19/2007 Document ID: 44E9O7HZ |
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