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What are the Recommendations for Using the PXIe-5122 or PXIe-5422 Below 10° C?

Hardware: Modular Instruments>>High-Speed Digitizers (Scopes)>>PXIe-5122, Signal Sources (AWG/FG/AO)>>Arbitrary Waveform and Function Generators>>PXIe-5422, Signal Sources (AWG/FG/AO)>>Arbitrary Waveform and Function Generators>>PXIe-5442

Problem:
The PXIe-5122 and the PXIe-5422  specifications mention that there may be special considerations for operation in ambient temperatures between 0 and 10° C for maximum data transfer rates. What are these considerations?

Solution:

PXI Express Topology

PXI Express uses PCI Express signaling and protocols for communication. A PCI Express system topology includes several different types of components:

• Root Complex. The root complex is the base of the PCI Express hierarchy. It connects the CPU and system memory to PCI Express I/O.
• Switch. A switch routes transactions among multiple PCI Express devices, other switches and the root complex. PCI Express communication is always point-to-point. A device communicates to a single switch. The switch then passes on the data to another switch, another PCI Express device or the root complex.
• Endpoint . An endpoint is a device that performs an I/O function, like a PXI Express module.

• Link. A link is a communication connection between two PCI Express elements. For example, a switch and an endpoint can form a link. A link consists of one or more lanes.
• Lane. A lane is a single transmit/receive pair connection between two PCI Express elements. Two devices can communicate data in both directions on a lane at the same time.

The following figure illustrates a link between two devices consisting of 4 lanes.

The number of lanes in a link is denoted as xn, where n is a number. All PCI Express devices must support x1 links. PCI Express devices may also support links of x2, x4, x8, x12, x16, and x32.

The data transfers on a lane can occur at 2.5 Gb/s or 5.0 Gb/s.

During initialization, the two devices of a link must negotiate the lane width and signaling speed that will be used for the link. This process is called link training. All devices must support x1 lane widths and 2.5 Gb/s signaling.

The actual throughput for a given system will be less due to protocol overhead, system topology, data transfers between other devices in the system and other components in the system.

Transfers between an I/O device and host memory usually travel through several PCIe links. Data transfer performance depends on the performance of each link. For example, if a PXI chassis is controlled with a x1 MXI Express link, the throughput to system memory may be limited by the x1 link.

As another example, consider a PXIe-1065 chassis. In this chassis, slots 7 and 8 support x4 PXI Express devices. Slot 7 and 8 each have a direct x4 PCIe path to the PXI controller. Slots 9-14 also support x4 PXI Express devices. However, data transfers for all of these slots (as well as PXI transfers for slots 15-18) all travel through a PCI Express switch on the backplane before transferring to the PXI controller. So all devices in slots 9-18 share the bandwidth available on the link between the backplane switch and the PXI controller.

These devices support x4, x2 or x1 links., and always uses 2.5Gb/s signaling rates. When one of these are installed in a PXIe slot that uses a x4 (or x8 or wider) PCIe switch, the device and the switch train to form a x4 link. (Currently all NI PXI Express chassis use x4 switches for all PXI Express slots). If the PXIe-5122 or PXIe-5422 is installed in a system that uses a x2 or x1 switch, the PXIe-5122 or PXIe-5422 trains to form a x2 or x1 link.

When these devices train with a x4 lane width, the maximum theoretical throughput of the link is 1,000 Mbytes/s. (Note that the PXIe-5122 generates data at 400 Mbytes/s (2 channels at 100 MS/s at 2 bytes per sample) and the PXIe-5422 generates data at 200 Mbytes/s (1 channel at 2 bytes per sample)).

If these devices train as x2 or x1, the PXIe-5122 and PXIe-5422 will still functions properly; and all operation specifications are unchanged. However, the maximum theoretical throughput of the link is decreased to 500 Mbytes/s (for x2) or 250 Mbytes/s (for x1). Again the actual transfer rate to host memory will be slower and depends on many other aspects of the system.

In rare cases, when a PXI system is turned on and the ambient temperature is below 10 °C, the PXIe-5122 and PXIe-5422 may detect a sufficient number of bit errors during training as x4, that the link reverts to a x2 or x1 width. If this occurs, you can still acquire data to on-board memory at the full specified acquisition rate of 100 MS/s on 2 channels. To retrain as a x4 width link in this case, you can keep the system powered on for 15 minutes (which is the specified warm-up time for the analog specifications to be valid for the device) and then reboot.

GetPXIExpressLinkWidth.exe and GetPXIExpressLinkWidth.vi (attached to this knowledge base) are utilities that display the lane width currently in use by a PXIe-5122 and PXIe-5422. Make sure NI-Scope version 3.3.1 (or later) and NI-FGEN 2.5 is installed in the system, before running this utility.

NOTE: This should only be done on a system that supports link widths of 4.  The 8103 controller for example, is an x1 controller and our device will always be trained as an x1 with this controller. The same is true with x1 MXI Express.

Related Links:

PCI Express - An Overview of the PCI-Express Standard

PCI Express and PXI Express Bandwidth Demos

PXI Express Specification Tutorial

Attachments:
GetPXIExpressLinkWidth.vi
GetPXIExpressLinkWidth.exe
GetPXIExpressLinkWidth_FGEN.vi
GetPXIExpressLinkWidth_FGEN.exe




Report Date: 06/15/2007
Last Updated: 11/11/2008
Document ID: 4AEB2ML1

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