Why does the TNT4882 T/L chip not send out the entire buffer? Hardware: GPIB
Problem: Register Level Programming: There is a small "glitch" in the logic of the TNT4882 T/L chip. The NEF bit (ISR3) de-asserts when the last byte in the FIFO is placed on the bus. This bit should de-assert after the last byte is ACCEPTED from all listeners. For a majority of applications, this is not a problem, but if you have a device which is very slow to accept the data, the FIFO may not really be empty. Instead, the FIFO may actually have 1 byte in it when it de-asserts the NEF bit. So, instead of having 16 words open in the FIFO, there are only 15 (and a half). If you write 16 words to the FIFO, the last byte may get "lost". Solution: When you are performing a write, only write 15 words to the FIFO when you don't see the NEF bit. Note: This problem only affects revision A of the TNT4882 ASIC (TNT4882-AQ). Related Links: Attachments:
Report Date: 03/18/1998 Last Updated: 07/24/2003 Document ID: 17HA3NQA |
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