PCI-6533 - The Input Group Ignores the Last Falling Edge on REQ When the Output Group Generates the ClockHardware: Digital I/O (DIO)>>High-Speed>>PCI-6533
Problem: When performing synchronous DIO, the input must latch data on a different clock edge than the output due to timing differences between the groups. Generally, this setup involves clocking the output group internally on the rising edge of the clock and wiring that clock to the input's REQ. The input is then configured for externally timed pattern acquisition, and data is latched on the falling edge of the clock. However, when both the input and output are latching the same amount of data in and out, the input group operation will hang with DIG_Block_Check returning "Remaining = 1" infinitely. This occurs, because the last falling edge on the clock, which is being generated by the output group, is being ignored by the input group. Solution: Make the number of points to output one greater than the number of points to acquire. Specifically, make the "Count" parameter on DIG_Block_Out one greater than the "Count" parameter for DIG_Block_In. Related Links: Attachments:
Report Date: 07/28/2000 Last Updated: 12/17/2002 Document ID: 1ZRF369V |
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