Single-Cycle Timed Loop FAQ for the LabVIEW FPGA ModulePrimary Software: LabVIEW Modules>>FPGA ModulePrimary Software Version: 1.0 Primary Software Fixed Version: N/A Secondary Software: N/A
Problem: FAQ: Single-Cycle Timed Loop (SCTL) in the LabVIEW FPGA Module Solution: What is the single-cycle Timed Loop? The single-cycle Timed Loop (SCTL) is a special use of the LabVIEW Timed Loop structure. Timed Loop structures are always SCTLs when used in an FPGA VI. When used with an FPGA target this loop executes all functions inside within one tick of the FPGA clock you have selected. The default selection is the 40 MHz FPGA global clock. You can use the SCTL with derived clocks to clock the loop at a rate other than 40 MHz. You cannot dynamically change the timing properties of the Timed Loop when used with an FPGA target, How much faster will programs execute using the SCTL? Using a traditional While Loop in your FPGA VI takes an absolute minimum of 3 ticks to execute each iteration. This is because of the enable chain used in the compiled FPGA VI. An explanation of the enable chain is beyond the scope of this document, but is used to ensure dataflow when the FPGA VI is compiled into a bitfile. Additionally, each function inside the While Loop will require at least one tick to execute, although functions will execute in parallel if there is no data dependency. With the SCTL, all functions inside the loop must execute within a single tick. The performance benefits of using a SCTL in your FPGA VI will vary depending on what is in the loop. If your code can compile successfully inside a SCTL instead of a normal loop, you will notice a marked performance improvement. Is the SCTL more real estate-efficient with FPGA resources? Yes. Because your logic is implemented combinatorially in hardware, the FPGA configuration generated by the code uses less resources. Instead of doing an add, saving the result, and then a multiply and saving the result, the SCTL does both in one tick and does not have to save the result in between. This conserves FPGA resources because no flip flop is needed between operations to save the result of each previous operation. Can all functions and structures be used inside the SCTL? No. Functions that take longer than one tick, such as analog I/O functions or any functions that wait cannot be used inside the SCTL. Also, if you have a chain of logic inside the loop that takes longer than one clock tick to execute, this logic cannot be used inside the SCTL and your VI will fail to compile. Sequence Structures may be placed within the SCTL, but will be removed from the code before it executes on the FPGA. Here is a list of some functions that cannot be used in a SCTL. Please refer to the LabVIEW Help for more information about SCTL support and timing information for individual VIs.
Yes. You can use shift registers or feedback nodes to allow logic to execute in parallel and pass data between subsequent iterations of the SCTL; thus, the entire logic chain iterates over multiple SCTL iterations. As with any parallel implementation in an FPGA VI, this uses additional FPGA resources. Will I get an error message if my logic inside the SCTL cannot execute in one tick? Yes. Typically, you will not receive any indication that there is a problem during edit time. When you attempt to compile the VI to VHDL code, you will receive a dialog box indicating the error(s). It will only take a few seconds for this box to appear. (The long VHDL compiling process does not begin). However, if the SCTL contains complex code that might or might not execute in one tick, the VHDL compiler will spend a long time trying to make it work and may eventually fail with a timing violation. Is the SCTL an advanced feature? Yes. While some tasks can be implemented very simply in the SCTL, some can be challenging. For example, implementing high-speed digital protocols cannot be done using wait functions if using the SCTL. You must use a state machine so that each iteration of the loop will take only one tick. The SCTL provides speed and efficiency for applications that require it, but can be tricky to use. In some situations it may be more appropriate to use the traditional While Loop. Can I use the SCTL with a faster global clock? Yes, however much fewer functions can be executed in a SCTL compiled at 80 MHz or above. Related Links: KnowledgeBase 3RCIP96K: How Do I Implement a Custom Single Cycle Timed Loop Rate in LabVIEW FPGA? KnowledgeBase 3W4CJJXJ: How Can I Optimize/Reduce FPGA Resource Usage? DeveloperZone Tutorial: Optimizing your LabVIEW FPGA VIs: Parallel Execution and Pipelining DeveloperZone Tutorial: FPGA Utilization Table KnowledgeBase 42RBUICW: Timed Loop Behavior on FPGA Target Attachments:
Report Date: 10/25/2006 Last Updated: 01/16/2009 Document ID: 42OGRRTQ |
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