Delay When Synchronizing 4472 DSA BoardsHardware: Modular Instruments>>Dynamic Signal Acquisition and Analysis (DSA)
Problem: Why does my DSA synchronization program take so long to run? Solution: This is most commonly observed when sampling at low rates, even if the total sample period is relatively small. When synchronizing multiple DSA boards, the timebases and sample clocks are phase locked through several shared clock signals. One of those clock signals, the sync pulse, is used to reset these devices and hence all sample clocks are phase-locked together. When the sync pulse is received, both boards enter into a hardware reset mode. In reset mode, the analog to digital converters (ADCs) of both boards are completely reset. As a result, both boards will start their new sample clocks within phase of one another. However, while the hardware reset is important for synchronization, it can take significant time in some circumstances. When both boards are sampling data at fast rates, the reset time is almost unnoticeable. However, at slow sampling rates, the reset time can be significant. For example, resetting the ADC can take as long as 16 seconds when sampling at 1 kHz. The simple solution is to increase the sample rate. Because the reset period requires a specified number of clock cycles, increasing sample clock frequency reduces the reset time. Related Links: KnowledgeBase 3PSGM42W: What Is a Phase-Locked Loop (PLL)? Developer Zone Tutorial: Performing Synchronized Vibration and Temperature Measurements Attachments:
Report Date: 03/01/2006 Last Updated: 11/30/2007 Document ID: 3V07H52W |
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