Problems Performing Double-Buffered Pattern Generation at the Rate Specified for the DIO-32HS with NI-DAQ 5.1 Primary Software: Driver Software>>NI-DAQPrimary Software Version: 5.1 Primary Software Fixed Version: 7.2 Secondary Software: N/A Hardware: Digital I/O (DIO)>>High-Speed>>DAQCard-6533, Digital I/O (DIO)>>High-Speed>>PCI-6534, Digital I/O (DIO)>>High-Speed>>DAQPad-6533 for IEEE 1394, Digital I/O (DIO)>>High-Speed>>PCI-DIO-32HS-T, Digital I/O (DIO)>>High-Speed>>PXI-6533, Digital I/O (DIO)>>High-Speed>>PXI-6534, Digital I/O (DIO)>>High-Speed>>PCI-6533, Digital I/O (DIO)>>High-Speed>>AT-DIO-32HS
Problem: I am using a function generator connected to the REQ1 pin to control the timing of a double-buffered, 16-bit pattern generation. It works flawlessly at 800 kilowords/second; however, when I increase the rate to 1 megaword/second and beyond, I observe stuttering at half-buffer boundaries. In other words, the board puts out the same word approximately 10 times and then continues normally until the next half-buffer boundary. I verified that I was feeding a clean TTL pulse train to the REQ1 pin. I am currently using NI-DAQ 5.1 with CVI. How can I correct this problem? Solution: First, upgrade to the latest version of NI-DAQ supported by your hardware and operating system (see links below) . The later versions of NI-DAQ improve bus transfers of data along with many other improvements. However, it is still possible at higher speeds for pattern I/O to not be able to keep up with the specified rate. Performance is highly system dependent. Make sure that the PCI bus does not have a lot of traffic across if from other devices. Also verify that as many system resources are free and that there are no unnecessary programs or applications running. If you find that you cannot consistently maintain the desired rate, try using an external FIFO (preferably a synchronous FIFO) and an external clock source. Configure the DIO-32HS for burst mode instead of pattern I/O, and have it handshake with the FIFO. The external device then interfaces to the FIFO (using the external clock source), instead of directly to the DIO-32HS. By using a FIFO, the DIO-32HS can talk as fast as possible in bursts to the FIFO, and the external device can talk at a steady rate to the FIFO, allowing the FIFO to handle lulls in the DIO-32HS communication. Related Links: Drivers and Updates: Current Versions: NI-DAQ NI-DAQ Driver Support for Windows Attachments:
Report Date: 03/30/1998 Last Updated: 06/17/2004 Document ID: 17TA3S0W |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
