Why is My Real-Time CPU at 100% When Reading from a DMA FIFO (FPGA)?Primary Software: LabVIEW Modules>>Real-Time ModulePrimary Software Version: 2009 Primary Software Fixed Version: N/A Secondary Software: N/A
Problem: I am reading data into my LabVIEW Real-Time program from an FGPA by using a Target to Host DMA FIFO. I can see in the Distributed System Manager that the Real-Time target's CPU usage nears 100%, which causes some starvation in processor-intensive applications. How can I resolve this issue? Solution: When reading from a DMA FIFO using the T to H FIFO.Read method with a significant timeout value, the Real-Time CPU will approach 100% if there is no data available in the FIFO. This behavior is expected. Because of the speed of most FPGA applications and the volume of data they produce, the data that arrives in the DMA FIFO should be read as soon as it is available. The Real-Time application, therefore, tells the Real-Time Operating System (RTOS) to check the DMA as fast and as often as possible under the aforementioned circumstances. This method of checking for data is called polling. Note: Unlike DMA FIFO's RT FIFO's can be configured as polling or blocking. Starvation of other threads is not a symptom of this expected behavior, but rather a symptom of an application that needs more careful consideration of thread timing. The appropriate way to resolve this issue is to use a preliminary T to H FIFO.Read method to programmatically check the DMA FIFO to see if the needed data is available before attempting to read the data. See Figure 1.
Related Links: LabVIEW 8.6 FPGA Module Help: Invoke Method Function Attachments:
Report Date: 05/02/2009 Last Updated: 07/22/2009 Document ID: 4X1GBJDK |
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