Toggling Rates for Digital DevicesHardware: Digital I/O (DIO)
Problem: The specifications for my digital device state that the maximum clock rate of my device is 50 MHz. However, when I output a toggled signal (0, 1, 0, 1, …), the frequency that I’m seeing on my oscilloscope is only half of that maximum clock rate. Why is this so? Solution: Two key terms to differentiate right away are the clock rate and toggle rate. They are defined in the context of digital outputs as follows:
For example, suppose you are running a PCIe-6537 at its maximum clock rate, 50 MHz. You write a digital pattern to the channel of 0, 1, 0, 1, etc. Since toggling a line requires two samples, one low and one high, the maximum toggling rate will be half of the maximum clock rate. In this case, the maximum toggle rate of the PCIe-6537 is 25 MHz. This is demonstrated below:
The important thing to remember is the difference between the clock rate and the toggle rate. If you are trying to generate clock signals on the digital data lines, the maximum toggle rate (one half of maximum clock rate) will be the maximum toggle rate. Keep in mind, you can export your sample clock to another device using the DAQmx Export Signal.vi or niHSDIO Export Signal.vi to export the sample clock to a PFI line or another valid terminal.
For more information on the High Speed Digital I/O product line, please refer to the product pages linked below: Related Links: High Speed Digital I/O Attachments:  - togglerate.JPG - togglerate1.JPG
Report Date: 12/01/2006 Last Updated: 12/04/2006 Document ID: 440HJLJQ |
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