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Why Do I Get Incorrect Emulation Behavior While Using the Single-Cycle Timed Loop?

Primary Software: LabVIEW Modules>>FPGA Module
Primary Software Version: 8.5
Primary Software Fixed Version: N/A
Secondary Software: N/A

Problem: When I run an FPGA application with several single-cycle Timed Loops in emulation mode, I get incorrect results.

Solution: This problem might be caused by too many single-cycle Timed Loops in memory, which results in some of the loops producing errors and returning default data from their output tunnels. If multiple FPGA VIs are in memory, close some of the VIs and try again. You also might be able to replace some single-cycle Timed Loops with While Loops for emulation purposes.

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Report Date: 08/24/2007
Last Updated: 08/28/2007
Document ID: 4BG8HU00

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