Handling HSDIO Data Delays Greater Than 100% Primary Software: Driver Software>>NI-HSDIOPrimary Software Version: 1.5 Primary Software Fixed Version: 1.5 Secondary Software: Other NI Software>>Digital Waveform Editor Hardware: Digital I/O (DIO)>>High-Speed>>PXI-6542, Digital I/O (DIO)>>High-Speed>>PXI-6551, Digital I/O (DIO)>>High-Speed>>PXI-6552, Digital I/O (DIO)>>High-Speed>>PXI-6561, Digital I/O (DIO)>>High-Speed>>PXI-6562, Digital I/O (DIO)>>High-Speed>>PCI-6541, Digital I/O (DIO)>>High-Speed>>PCI-6542, Digital I/O (DIO)>>High-Speed>>PCI-6551, Digital I/O (DIO)>>High-Speed>>PCI-6552, Digital I/O (DIO)>>High-Speed>>PCI-6561, Digital I/O (DIO)>>High-Speed>>PCI-6562, Digital I/O (DIO)>>High-Speed>>PXI-6541
Problem: NI-HSDIO devices (654x, 655x, 656x) provide a property called Data Position.Delay to account for delays caused by driving data over a transmission line. However, the programmable delay has a maximum range of 100% of a sample clock cycle. How can a delay of greater than 100% be accommodated for real-time hardware comparison applications? Solution: In situations with data delays exceeding 100%, the comparison waveform can simply be resampled with a 2:1 interpolation. This duplicates each sample cycle-by-cycle, adding a "natural" 100% data delay to the waveform. For example, if we need a 124% delay in this comparison waveform: We can first interpolate it 2:1. Each sample is duplicated, and the resultant waveform is shown: This adds an effective 100% delay to each data sample. Using this waveform, a program can be written with a data position delay of 24% to achieve the full 124% delay that is desired. Related Links: Attachments:  
Report Date: 10/23/2006 Last Updated: 10/27/2006 Document ID: 42MATJD3 |
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