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FPGA Compile Error: Cannot find input file "toplevel_gen_map.ncd"

Primary Software: LabVIEW Modules>>LabVIEW FPGA Module
Primary Software Version: 1.0
Primary Software Fixed Version: N/A
Secondary Software: N/A

Problem:
Why do I get the following error when I try to compile my FPGA code: FPGA Compile Error: Cannot find input file "toplevel_gen_map.ncd"?

The compile time also takes an unusually long time.

Solution:
The cause of this error may be due to a configuration of a large FIFO depth. Decreasing the FIFO depth to 8191 (the recommend amount) will significantly decrease the compile time and removes the error.

If a bigger FIFO is needed for faster data transfer rates, use the method node on the Host VI to increase its FIFO depth. This will increase the amount of memory available on the host VI. See related links.

Related Links:
Knowledgebase 2ELD9UKN: Real-Time FIFO Frequently Asked Questions

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Report Date: 06/10/2009
Last Updated: 06/12/2009
Document ID: 4Y991V45

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