What is the Definition of Logic Cells, Logic Slices, Configurable Logic Blocks and Gates in Regards to FPGA Devices?Hardware: Reconfigurable I/O (RIO)>>R Series>>PXI-7831R
Problem: The NI R Series Intelligent DAQ User Manual says that it has a combination of logic slices and logic cells. What do these terms mean? Solution: The Virtex II FPGA: A logic cell consists of a lookup table, a flip flop, and connection to adjacent cells. The lookup table uses combinatorial logic to implement a 4-input expression (and, or, nand, addition, etc.) A logic slice consists of 2 logic cells. Xilinx counts closer to 2.25 logic cells per slice because they can do more per configurable logic block (CLB) than other architectures. A configurable logic block (CLB) consists of 4 slices. This combined architecture gives benefits in the final system such as increased performance of logic execution. The Xilinx FPGA also includes other components such as 44 memory blocks, each providing 2 KB of storage, and multipliers. The number of gates is number representing the combination of memory banks, cells, multipliers, etc. It is important to note that the efficiency of a gate in an FPGA is not equivalent to that of a gate in an ASIC. For example, a 1M gate FPGA is roughly equivalent to a 100K gate ASIC. The Virtex-5 FPGA: The definition of a logic slice and cell is slightly different for the Virtex-5. It has 2 slices per CLB and has 4 6-input look up tables. Additionally, the Virtex-5 has 4 flip-flops per slice. Related Links: Product Manuals: NI R Series Intelligent DAQ Manual Products & Services: LabVIEW FPGA Module Developer Zone Tutorial: Resource Utilization Statistics for FPGA VIs Attachments:
Report Date: 07/31/2003 Last Updated: 06/09/2009 Document ID: 2ZUA4DFL |
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