Incorrect Conversion Time Using The NI 9205 ModuleHardware: CompactDAQ>>Analog Input Modules>>NI 9205 D-Sub
Problem: I have a CompactRIO which uses an NI 9205 module to sample analog voltages in FPGA interface mode. When I read a single channel with this module, I am able to achieve the minimum time between conversions chosen in the module properties. But when I attempt to read two different channels using separate IO nodes, my conversion time is 6 times the minimum time between conversions. Why can I not achieve the expected conversion time between samples? Solution: It is important to note that every physical conversion will take approximately the minimum time between conversions chosen in the module properties. So if we choose the default minimum time between conversions of 4µs, a single conversion will take only the expected 4µs, and two conversions will require 8µs. However, if you use two separate IO nodes to read two different channels from the NI 9205 module as depicted below, you will find that the nodes require 24µs to return their samples. This is 3 times longer than expected based upon the minimum time between conversions chosen.  This is because the NI 9205 uses an analog to digital converter that utilizes a two element deep pipeline. In order to achieve the maximum performance from this analog to digital converter, this pipeline must be managed. The FPGA IO node attempts to manage the pipeline for you, but in order for it to be successful, you must include both channels within the same IO node as seen below. Using the same IO node will create the logic required to automatically load alternating sample requests for the two channels into the pipeline.  If you do not include the two channels in the same IO node, each IO node instance will attempt to manage the pipeline. This will cause each IO node, upon execution, to first flush the other channels requests from the pipeline, and then fill the pipeline with duplicate requests for its own channels samples. It will then require three conversions to produce the correct sample. This process is then repeated for the other IO node which will total 6 conversions per loop iteration. This same effect will also be seen if the two IO nodes are used in different loops because the pipeline is a shared resource, and each node will need to wait for the other to complete operations on the pipeline. Related Links: KnowlegeBase 4MJ7Q2KG: Programmatically Setting the NI 9205 Voltage Range Attachments:
Report Date: 01/10/2009 Last Updated: 01/15/2009 Document ID: 4T9HQMMO |
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