Why Won't My PXI-7830R VI Compile When Using a Clock Derived From PXI CLK10? Primary Software: LabVIEW Modules>>FPGA ModulePrimary Software Version: 8.2 Primary Software Fixed Version: N/A Secondary Software: N/A Hardware: Reconfigurable I/O (RIO)>>R Series>>PXI-7830R
Problem: When I use PXI CLK10 MHz Clock as my base clock in a PXI-7830R VI and try to compile, I get error messages similar to the following: ERROR:HDLParsers:3313 - "C:/NIFPGA80/srvrTmp/LOCALH~1/TESTPX~1/toplevel_gen.vhd" Line 1449. Undefined symbol 'dio_194'. Should it be: dio_14? Solution: This is a known issue with using a 7830R in LabVIEW 8.0 or 8.2 and specifying the PXI CLK10 as your base clock. It has been shown to happen with the NI-RIO 2.0 and 2.1 drivers. Upgrading to LabVIEW 8.5 and NI-RIO 2.3 or later solves the issue. Related Links: Attachments:
Report Date: 08/15/2007 Last Updated: 11/11/2007 Document ID: 4CEM1N3U |
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