Using an External Clock with Finite Pattern I/O Hardware: Digital I/O (DIO)>>High-Speed>>AT-DIO-32HS
Problem: How do I use an external clock with finite pattern I/O mode? Solution: When using an external clock with finite pattern I/O mode, a clock edge is required after the final edge to flush the data out of the DIO ASIC and into the computer memory. By default in LabVIEW, the REQ polarity is active low; this means data is either latched or outputted on the falling edge of the clock. Because an additional clock edge is required after the final data latching or data output edge to flush all the data out to the PC memory, you must supply an extra pulse. For example, in Diagram 1 (below) the device is configured for finite pattern input with a buffer size of 2. Since the REQ polarity is unchanged in LabVIEW, data is latched on the falling edges of the clock. Once two falling edges are received by the 653x device, on the next rising clock edge, the DIO ASIC flushes out the data to the PC memory. For applications where it is not possible to supply the extra clock edge, you may set the REQ polarity to active high (latch on rising edge). Using the same example where the 653x device is configured for finite buffer pattern input with a buffer size of 2, this time the REQ polarity is changed to active high (see Diagram 2 below). Data is latched on the rising edges of the clock. The falling edge on the second clock pulse flushes all the data out of the DIO ASIC. You are not expected to supply an extra clock edge in this case. Related Links: Attachments:
Report Date: 06/21/2002 Last Updated: 08/25/2006 Document ID: 2MKG9REV |
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