When Does the VXI-MXI-2 De-Assert the SYSRESET* Line on the VXI Backplane?Hardware: VXI/VME/MXI>>MXI Interfaces>>VXI-MXI-2
Problem: When does the VXI-MXI-2 de-assert the SYSRESET* line on the VXI backplane? Solution: The SYSRESET* is required to stay asserted for a minimum of 200 ms after: (a) +5V power rail stabilizes AND (b) after the ACFAIL line de-asserts. After both events have completed, the SYSRESET* line is de-asserted by the controlling MITE chip on the VXI-MXI-2 after 2^24 cycles of this chip. This is so both events have at least a 200 ms delay before the de-assert of SYSRESET*. This is per Rule 5.1 and Figure 5-5 of the VME specification, which governs this behavior. Permission 5.4 of the VME specification states that when SYSRESET* goes low, any board that requires more than 200 ms to complete its initialization may turn on its SYSRESET* driver low to maintain the SYSRESET* low for the required period. Therefore, if a device requires more than a 200ms delay to complete its initialization, it is the responsibility of the device to start driving SYSRESET* until it is properly initialized. If you are using an external CLK10 source because of timing issues, the CLK10 source will not output its signal before the SYSRESET* line is de-asserted. This can cause some instruments in the chassis to keep their SYSFAIL lines asserted. In order to clear this SYSFAIL state, it is possible to manually reset the VXI-MXI-2 with the reset button on the front panel, or send a command to the VXI-MXI-2 controller to reassert the SYSRESET* line. Both methods will cause the VXI-MXI-2 and all instruments in the chassis to reset, thus re-asserting the SYSRESET* line. Related Links: Attachments:
Report Date: 02/07/2003 Last Updated: 09/16/2003 Document ID: 2U6G2PUD |
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