Special Considerations for PFI0 on the PXI-6682 Primary Software: Driver Software>>NI-SyncPrimary Software Version: 3.0 Primary Software Fixed Version: N/A Secondary Software: N/A Hardware: PXI/CompactPCI>>Platform Modules>>PXI-6682
Problem: PFI0 seems to behave inconsistently. Sometimes I get an immediate timestamp even if my input hasn't changed. The same problem happens if I connect PFI0 to a destination, the initial state seems to be floating. Do I have a problem with PFI0? Solution: There is no problem with PFI0. PFI0 is a dual purpose terminal, capable of performing digital I/O like the other PFI lines while also being capable of receiving IRIG-B AM and DC inputs, special care is taken to protect the digital circuitry when PFI0 is being used as an IRIG-B AM input. This is achieved with a normally-open solid-state relay (SSR), which is closed only when digital operations for the line are enabled through the API. Digital operations include setting up routes in which PFI0 is the source or the destination, enabling timestamping for PFI0, and scheduling synchronized future time events or clocks for PFI0. The SSR has a 5ms open and close time. Therefore, special care must be taken when using PFI0 to ensure correct operation when the SSR is switching. For example, if PFI0 is being externally pulled to a logic high voltage, and timestamping is enabled for PFI0, the slow close time of the SSR will make the voltage seen by the timestamping unit rise very slowly which could result in an incorrect number of timestamped edges. Likewise, when scheduling an output high logic level using an immediate future time event will result in a very slow rising edge output on PFI0, which may cause incorrect behavior in the external receiving circuitry. These issues only exist when the SSR is switching. The SSR will switch when PFI0 is first programmed for a digital operation after the line was being used for a different operation. For example, after booting up, the SSR will be open, and will close if a synchronized future time event is scheduled for PFI0 (whether it is an immediate future time event or not). The SSR will remain closed until future time events are disabled for this line, so subsequent future time events, even immediate future time events will operate properly and will not be affected by a slow rise or fall time. However, if the line is configured for a different operation, like, for example, being the source of a route, or timestamping, the SSR will open when future time events are disabled, and close again when the new operation is enabled. If you want to use the line to generate synchronized future time events again, the SSR will open when the previous operation is disabled, and close again when synchronized future time events are enabled. That first future time event is subject to the slow closing time of the SSR, but the subsequent events are not. It is recommended that the first future time event be either more that 5ms in the future, or be logic low. To avoid issues due to the SSR switching, adhere to the following guidelines:
Related Links: Products and Services: PXI-6682 Attachments:
Report Date: 10/10/2007 Last Updated: 10/25/2007 Document ID: 4E9BT88P |
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