Code Generation Error 61056: Invalid Arbitration for Single-Cycle Timed LoopPrimary Software: LabVIEW Modules>>LabVIEW FPGA ModulePrimary Software Version: 1.0 Primary Software Fixed Version: N/A Secondary Software: N/A
Problem: During the code generation process of compiling my FPGA VI I get an error 61056 that states: Component xyz has invalid arbitration for Single-Cycle Timed Loops. How do I resolve this?Solution: Arbitration refers to the additional logic added to handle instances when a shared resource may be accessed from multiple places at the same time. This extra logic takes more than one cycle to execute and is not available for use in a Single-Cycle Timed Loop (SCTL). Examples of shared resources that require arbitration include:
The error above will be encountered if more than one instance of one of the above resources is referenced inside a SCTL, and arbitration is enabled. The example below shows a case when this might happen. The case structure has a reference to DIOPORT0 in both cases. If arbitration is enabled, this code will cause error 61056, even though the two references will never run concurrently. By default, arbitration is set to Never Arbitrate in the I/O Properties, which is found by right-clicking the I/O in your Project Explorer and selecting Properties » Advanced Code Generation. If you recieve this error, check to make sure that this option is set to Never Arbitrate. However, before doing this, you should make sure that the resource you are using can never be called more than once in a SCTL.
Related Links: 3UF9NAXJ: Code Generation Error 61056: Sub VI is Non-Reentrant, is in a Single-Cycle Timed Loop, and Has More Than One Caller Attachments:
Report Date: 02/16/2006 Last Updated: 08/08/2011 Document ID: 3UF966XJ |
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