Creating a Delayed, Retriggerable, and Finite Pulse Generator

Issue Details

I want to generate a delayed, retriggerable, finite pulse train. When I generate a pulse train of one pulse, I get the expected behavior. The figure below shows this behavior with a delayed retriggerable single pulse 1kHz pulse train + 1ms initial delay. 



When I try to do a delayed, retriggerable finite pulse train generation, the delay occurs properly only at the first trigger but not at the others. The second figure below demonstrates this behavior with a delayed retriggerable pulse train at 1kHz + 1ms initial delay. For later triggers, the counter acts immediately and the finite pulse train is triggered with no delay even when the Low Time is set. How can I correct this?

Solution

Devices with the STC3 Timing Engine:
Use a property node to enable the initial delay on retriggerable pulses. This property can be found under the DAQmx Channel » Counter Output » General Properties » More » Enable Initial Delay On Retrigger. 

Older Devices:
You will need to use two counters on older chipset devices. Configure the first counter (ctr0) to generate a continuous pulse train on its OUT pin. This pulse train is then gated by the second counter (ctr1). Using the DAQmx Trigger property node, you can configure the continuous pulse train to pause when the internal output of the second counter goes low. This means that the only visible pulses will be when ctr1 is high, which is gating the continuous pulse train to be configured as a finite generation.

Additional Information

The figure below illustrates an example of how to do the described solution. The number of pulses that will be seen is configured by dividing the number of desired pulses (5) by the frequency of the continuous pulse train (1000 Hz). This gives a high time for the gating counter of 5 ms. The low time is also configured to be 5 ms. This means that when the trigger is received, which is PFI 1 in this case, there will be 5 ms of low time on the gate before the 5 pulses are seen. This effectively creates a delay for each retriggerable generation.