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Creating a Delayed, Retriggerable and Finite Pulse Generator

Primary Software: Driver Software>>NI-DAQmx
Primary Software Version: 8.5
Primary Software Fixed Version: N/A
Secondary Software: N/A
Hardware: Multifunction DAQ (MIO)>>E Series

Problem: I want to perform a delayed, retriggerable, finite pulse train generation. When I generate a single finite pulse from a retriggerable counter (Fig. 1 - Delayed retriggerable single pulse), it behaves differently than generating a finite pulse train from a retriggerable counter (Fig. 2 - Delayed retriggerable pulse train).

When I generate a pulse train of one pulse, I get the expected behavior according to: Knowledgebase 3GSKKKR6: Different Counter Retrigger and Initial Delay Behavior in Traditional (Legacy) NI-DAQ and DAQmx. When the first trigger occurs, the counter will wait an Initial Delay in the Idle State before it changes state. For all subsequent triggers, the counter starts in the Idle State, then switches to the non-Idle state immediately (regardless of the Initial Delay). In the case of Fig. 1, each triggered subsequent pulse has a Low Time specified that is less than the Initial Delay. With a single pulse, you can also set the Low Time equal to the Initial Delay and it will appear with an offset of this value on each triggered pulse.

Fig. 1 - Delayed retriggerable single pulse (1kHz pulse train + 1ms initial delay)

When I try to do a delayed, retriggerable finite pulse train generation, the delay occurs properly only at the first trigger but not at the others. For latter triggers, the counter acts immedicately and the finite pulse train is triggered with no delay even when the Low Time is set.

Fig. 2 - Delayed retriggerable pulse train (1kHz pulse train + 1ms initial delay)

How can I setup this issue?

Solution:
In order to setup a delayed, retriggerable finite pulse train with more than one pulse, two counters need to be used.

The first counter (ctr 0) should be configured to generate a continous pulse train on its OUT pin. This pulse train is then gated by the second counter (Ctr 1). Using the DAQmx Trigger property node, you configure the continuous pulse train to pause when the internal output of the second counter goes low. This means that the only visible pulses will be when ctr 1 is high, which is gating the continuous pulse train to be configured as a finite generation.

In the following picture, the number of pulses that will be seen is configured by dividing the number of desired pulses (5) by the frequency of the continuous pulse train (1000 Hz). This gives a high time for the gating counter of 5 ms. The low time is also configured to be 5 ms. This means that when the trigger is received, which is PFI 1 in this case, there will be 5 ms of low time on the gate before the 5 pulses are seen. This effectively creates a delay for each retriggerable generation.