Decreased Counter Measurement Resolution With Digital Filtering Hardware: Counter/Timers (TIO)>>Devices, Multifunction DAQ (MIO)>>M Series
Problem: Why does my counter resolution decrease when I use a digital filter on a counter input task with an NI M-Series or TIO device? Solution: This is expected behavior. The input of any PFI line can be passed through a simple digital debouncing filter. The filter operates off a filter clock and a fast internal sampling clock. The filter circuit samples the signal on the PFI line on each rising edge of the sampling clock. A change in the signal is propagated only if it maintains its new state for at least the duration between two consecutive rising edges of the filter clock timebase. The frequency of the filter clock timebase determines whether a transition in the signal may propagate or not. The function of the internal sampling clock is to increase the sampling rate and prevent aliasing.  As shown in the above diagram, although the signal is sampled on the maximum timebase clock, the incoming signal only becomes valid if it is detected by two positive edges of the filter clock. The result is that the resolution of the incoming signal is determined by the filter clock, not the maximum timebase.
The frequency of the filter clock is determined by the minimum pulse width you set for the digital filter. So, if you are using the filter for debouncing, set the minimum pulse width for the digital as small as possible in order to achieve high resolution for the incoming signal. Related Links: Knowledgebase 3VDG0388: Enabling the Digital Filters for Counter/Timer Devices in NI-DAQmx Knowledgebase 30KHKH6I: How Do I Remove Glitches or Add a Debounce Filter to My Digital Signal? Knowledgebase 3P0COO88: Resolution of Period Measurement with the PCI-6624 Attachments:
Report Date: 08/17/2007 Last Updated: 03/07/2008 Document ID: 4CG86RM6 |
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