Synchronization with a High Speed Digital Input/Output (HSDIO) Board Hardware: Digital I/O (DIO)>>High-Speed
Problem: How can I Synchronize my HSDIO Board with Other Devices? Solution: National Instruments high speed digital input-output boards can be synchronized with multiple devices and to varying degrees, depending on the specific device to which they are synchronized. For example, when synchronizing HSDIO boards with other SMC (Synchronization and Memory Core) modular instruments, boards can be synchronized to within 500ps (using T-Clk), the jitter of the PXI 10MHz system reference clock. However, when synchronizing an HSDIO board with devices that do not use the SMC architecture, this time can be as long as an entire sample period. Ideally, synchronization of modules is done by sharing a sample clock and star trigger. However, depending on the specific devices being used, this is not always possible. The following document describes synchronization capabilities of NI HSDIO modules and how these are implemented in software. NI-TClk: When synchronizing HSDIO boards with other SMC devices, TClk technology provides the highest level of synchronization. This technique requires all devices to Phase-Lock Loop to the PXI 10MHz system reference clock and share a start trigger on a PXI trigger line. In software, this is done with the TClk VI’s. The result is digital generation or acquisition with all devices synchronized to within 500ps, the jitter of the PXI system reference clock. The LabVIEW shipping example Multi-Device Dynamic Acquisition (TClk) illustrates how to use the TClk VIs to synchronize multiple HSDIO modules. Some of these VI's are shown below:
In cases where TClk is not an option, boards can be synchronized by sharing a sample clock. With this configuration, one board will operate as the master and the others will operate as the slaves. Using the HSDIO board as the master device requires it to output its sample clock to the other devices through one of two destinations:
Sharing sample clocks is only effective when all devices are sampling or generating data at the same rate. Thus, when using multiple devices at different sampling rates, greater synchronization can be achieved by sharing a 10 MHz reference clock. Ideally, all devices will use the PXI 10 MHz system reference clock. However, some devices are not capable of this and require a clock to be routed to them. Thus, the HSDIO board can operate as a master (routing a reference clock) or slave (importing a reference clock). When operating as a master, the timebase is routed to ClkOut on the front connector. When the HSDIO board operates as a slave, it receives a reference clock at one of three different sources. These are:
The final synchronization option for HSDIO boards is a shared start trigger. This method ensures that all boards will be synchronized to within one period of the sampling rate, even if the boards do not share a timebase or sample clock. HSDIO boards can receive a digital start trigger on any of the RTSI, PXI_Trig, or PXI_STAR trigger lines. In software, configuring a digital start trigger can be done with the niHSDIO Configure Trigger vi. In addition, HSDIO boards can export a digital start trigger on any RTSI, PXI_TRIG trigger lines. Thus, the board is able to start generation or acquisition simultaneously with another module. A shared start trigger can be configured with the niHSDIO configure start trigger VI, shown below:
Related Links: Developer Zone Tutorial: National Instruments T-Clock Technology for Timing and Synchronization of Modular Instruments Product Reference: NI-TClk Comparison of Terminology between NI-TClk, NI-HSDIO, NI-SCOPE, and NI-FGEN Products & Services: High-Speed Digital I/O Devices Attachments:  - config_sample_clk.GIF - tclk_sync.GIF - export_signal.GIF - config_reference_clock.GIF - configure_trigger.GIF - config_ref_clock.GIF
Report Date: 02/13/2006 Last Updated: 03/14/2008 Document ID: 3UCA272W |
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