Why Do I Get A Resource Interface(s) Used in Multiple Clock Domains Error? Primary Software: LabVIEW Modules>>FPGA ModulePrimary Software Version: 8.5 Primary Software Fixed Version: N/A Secondary Software: N/A
Problem: I am compiling an FPGA VI for my CompactRIO system. I am using two digital I/O modules with one digital module being used in a timed loop using a derived clock, and the other module being used in a parallel while loop. When I try to compile I receive an error similar to the following:
Why am I receiving this error? If I use a timed loop that utilizes the default clock, no error occurs. Solution: This error would be expected if you were trying to access lines in the same module at different rates because the timing clock for the IO is shared throughout the module. However, this error can also occur between different modules, such as the 9485 and 9411 because these and other modules share communication lines on the FPGA backplane and the clock speed of one module effects the other. To eliminate this error, use loops that reference the same clock and use a counter to sample at a lower rate. Or, sample both lines at the same rate and decimate the received data. For example, to sample DIO1 at 1MHz, and DIO2 at 40MHz, your code would look similar to this:
Other derived clocks can be used for the timed loops, so long as the other loops accessing these shared resources are also referencing the same derived clock. Note: If your timed loop uses the default clock and you have a while loop in parallel, the code will compile because the while loop will be compiled referencing the default clock as well. Related Links: KB 3RCIP96K: How Do I Implement a Custom Single Cycle Timed Loop Rate in LabVIEW FPGA? Attachments:
Report Date: 01/16/2008 Last Updated: 01/17/2008 Document ID: 4HFIIKKO |
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