What Is a Phase-Locked Loop (PLL)?Hardware: Multifunction DAQ (MIO)>>M Series, PXI/CompactPCI>>Platform Modules>>PXI-6651, PXI/CompactPCI>>Platform Modules>>PXI-6652, PXI/CompactPCI>>Platform Modules>>PXI-6653
Problem: What is a phase-locked loop (PLL)? How does a phase-locked loop work? What hardware connections are required for PLL circuits? Solution: A phase-locked loop (PLL) is a feedback circuit designed to allow one circuit board to synchronize the phase of its on board clock with an external timing signal. PLL circuits operate by comparing the phase of an external signal to the phase of a clock signal produced by a voltage controlled crystal oscillator (VCXO). The circuit then adjusts the phase of the oscillator’s clock signal to match the phase of the reference signal. Thus, the original reference signal, and the new signal are precisely in phase with each other. Phase-lock looping is an extremely powerful synchronization technique when performing data acquisition because it allows multiple boards to lock to a shared reference signal. As a result, these boards can synchronize the phase of their internal 80 MHz or 20 MHz timebase and thus, their sample clocks. Because the phase of each sample clock is synchronized, each board can take a measurement at precisely the same instant. A good visual example of this is shown in the following figure from the M series user manual.  Figure 1: M Series Timing Sources This block diagram shows how the PLL is used to derive the rest of the timing signals in the M Series DAQ devices. Figure 2 shows a block diagram of the PLL that is used on the M Seris DAQ devices.  Figure 2: PLL Block Diagram The actual programming techniques required to synchronize the sample clocks of multiple boards through a phase-locked loop depends on the type of hardware in use. With PCI-based products (M-Series PCI DAQ boards, PCI digitizers, etc.), all synchronization is conducted by sharing signals through Real Time System Integration (RTSI) timing and trigger lines connected by a RTSI cable. In this scenario, one board will operate as the master and export its internal clock over a RTSI line to the slave boards. With PXI-based products the same method can be applied as is used with PCI cards, however, PLL synchronization is more commonly conducted by synchronizing each board’s clock to the PXI Chassis 10 MHz clock, which is built in to the backplane of the chassis and accessable through PXI Trigger lines. For instrument-specific information on phase locked looping, see the links below. Related Links: Developer Zone Tutorial: M Series Synchronization with LabVIEW and NI-DAQmx Developer Zone Tutorial: Synchronization and Memory Core -- a Modern Architecture for Mixed-Signal Test Developer Zone Tutorial: National Instruments T-Clock Technology for Timing and Synchronization of Modular Instruments Developer Zone Tutorial: Setting Time Measurements of a PLL Chip Developer Zone Tutorial: What Clock Error Means to Your Measurement System Developer Zone Tutorial: PXI Specification Tutorial KnowledgeBase 379AM3FE: What are the Valid Phase-Lock Looping Reference Clock Parameters for Modular Instruments? Attachments:
Report Date: 09/29/2005 Last Updated: 06/30/2009 Document ID: 3PSGM42W |
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