Why Does My FPGA Compile Give An OVERMAPPED Error When Compiling?
Primary Software Version: 8.0
Primary Software Fixed Version: N/A
Secondary Software: N/A
I have compiled my code successfully in the past, but I recently added some code and now I'm getting an OVERMAPPED error in the mapping phase of my LV FPGA compile. What is causing this?
OVERMAPPED essentially means that your code requires more resources than are available on the FPGA hardware. Errors like these can be found in the FPGA error log file:
A typical OVERMAPPED error at the end of the log file typically looks like this:
Slices are a fundamental unit of resources on the FPGA. If your code, after optimization by the compiler, requires more slices than are available on your FPGA then the code will not fit and you will get a compile error. For more information on Slices and how to reduce your FPGA usage, see the KnowledgeBase articles linked below.
KnowledgeBase 3W4CJJXJ: How Can I Optimize/Reduce FPGA Resource Usage?
KnowledgeBase 2ZUA4DFL: What is the Definition of Logic Cells, Logic Slices, Configurable Logic Blocks and Gates?
KnowledgeBase 4CE49HPL: How Do I View the Last "Successful Compile Report" from the LabVIEW FPGA Module?
Report Date: 04/29/2004
Last Updated: 02/04/2014
Document ID: 38S79L9U